74HCT534_3| Datasheet

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74HCT534
5 V octal D-type flip-flop; positive-edge trigger; inverting; 3-state
Rev. 03 -- 18 October 2004 Product data sheet

1. General description
The 74HCT534 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HCT534 is specified in compliance with JEDEC standard no. 7A. The 74HCT534 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and inverting 3-state outputs for bus oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops. The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of the 8 flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. The 74HCT534 is functionally identical to the 74HCT374, but has inverted outputs.

2. Features
s 3-state inverting outputs for bus oriented applications s 8-bit positive-edge triggered register s Common 3-state output enable input.

3. Quick reference data
Table 1: Quick reference data GND = 0 V; Tamb = 25 C; tr = tf = 6 ns. Symbol Parameter Conditions CL = 15 pF; VCC = 5 V CL = 15 pF; VCC = 5 V Min CL = 50 pF; VCC = 4.5 V
[1] [2]

Typ 13 40 3.5 19

Max -

Unit ns MHz pF pF

tPHL, tPLH propagation delay CP to Qn fmax CI CPD
[1]

maximum clock frequency input capacitance power dissipation capacitance per flip-flop

CPD is used to determine the dynamic power dissipation (PD in uW). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF;