74HC_HCT138_3| Datasheet

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74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
Rev. 03 -- 23 December 2005 Product data sheet

1. General description
The 74HC138; 74HCT138 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The 74HC138; 74HCT138 decoder accepts three binary weighted address inputs (A0, A1 and A3) and when enabled, provides 8 mutually exclusive active LOW outputs (Y0 to Y7). The 74HC138; 74HCT138 features three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the 74HC138; 74HCT138 to a 1-of-32 (5 lines to 32 lines) decoder with just four 74HC138; 74HCT138 ICs and one inverter. The 74HC138; 74HCT138 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Not used enable inputs must be permanently tied to their appropriate active HIGH- or LOW-state. The 74HC138; 74HCT138 is identical to the 74HC238; 74HCT238 but has inverting outputs.

2. Features
s s s s s s Demultiplexing capability Multiple input enable for easy expansion Complies with JEDEC standard no. 7A Ideal for memory chip select decoding Active LOW mutually exclusive outputs ESD protection: x HBM EIA/JESD22-A114-C exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V s Specified from -40 C to +85 C and from -40 C to +125 C