74HC_HCT238_3| Datasheet

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74HC238; 74HCT238
3-to-8 line decoder/demultiplexer
Rev. 03 -- 16 July 2007 Product data sheet

1. General description
74HC238 and 74HCT238 are high-speed Si-gate CMOS devices and are pin compatible with Low-Power Schottky TTL (LSTTL). The 74HC238/74HCT238 decoders accept three binary weighted address inputs (A0, A1, A2) and when enabled, provide 8 mutually exclusive active HIGH outputs (Y0 to Y7). The 74HC238/74HCT238 features three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every output will be LOW unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the "238" to a 1-to-32 (5 lines to 32 lines) decoder with just four "238" ICs and one inverter. The "238" can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Unused enable inputs must be permanently tied to their appropriate active HIGH or LOW state. The 74HC238/74HCT238 is similar to the 74HC138/74HCT138 but has non-inverting outputs.

2. Features
I I I I I I I Demultiplexing capability Multiple input enable for easy expansion Ideal for memory chip select decoding Active HIGH mutually exclusive outputs Multiple package options Complies with JEDEC standard no. 7A ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V I Specified from -40 C to +85 C and from -40 C to +125 C