74LVC377_5| Datasheet

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74LVC377
Octal D-type flip-flop with data enable; positive-edge trigger
Rev. 05 -- 21 February 2005 Product data sheet

1. General description
The 74LVC377 is a low-voltage, Si-gate CMOS device superior to most advanced CMOS compatible TTL families. The 74LVC377 has eight edge-triggered D-type flip-flops with individual inputs (D) and outputs (Q). A common clock input (CP) loads all flip-flops simultaneously when data enable input (E) is LOW. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. Input E must be stable only one set-up time prior to the LOW-to-HIGH transition for predictable operation.

2. Features
s s s s s s Wide supply voltage range from 1.2 V to 3.6 V Inputs accept voltages up to 5.5 V CMOS low power consumption Direct interface with TTL levels Output drive capability 50 transmission lines at 125 C Complies with JEDEC standard: x JESD8-B/JESD36 (2.7 V to 3.6 V) s ESD protection: x HBM EIA/JESD22-A114-B exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V s Specified from -40 C to +85 C and from -40 C to +125 C

3. Quick reference data
Table 1: Quick reference data GND = 0 V; Tamb = 25 C. Symbol Parameter tPHL, tPLH CI fmax Conditions Min VCC = 3.3 V Typ 4.6 5.0 330 Max Unit ns pF MHz propagation delay CP to VCC = 3.3 V; CL = 50 pF; Qn RL = 500 input capacitance maximum clock frequency