74LVC544A_3| Datasheet

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74LVC544A
Octal D-type registered transceiver; inverting; 3-state
Rev. 03 -- 11 May 2004 Product data sheet

1. General description
The 74LVC544A is a high-performance, low-power, low-voltage, Si-gate CMOS device superior to most advanced CMOS compatible TTL families. The 74LVC544A is an octal registered inverting transceiver containing two sets of D-type latches for temporary storage of the data flow in either direction. Separate latch enable inputs (LEAB and LEBA) and output enable inputs (OEAB and OEBA) are provided for each register to permit independent control of inputting and outputting in either direction of the data flow. The 74LVC544A contains eight D-type latches, with separate inputs and controls for each set. For data flow from pins A to B, for example, the A to B enable input (pin EAB) must be LOW in order to enter data from pins A0 to A7 or take data from pins B0 to B7. With pin EAB LOW, a LOW signal on the A to B latch enable input (pin LEAB) makes the A to B latches transparent; a subsequent LOW-to-HIGH transition on pin LEAB puts the A data into the latches where it is stored and the B outputs no longer change with the
A inputs. With pins EAB and OEAB both LOW, the 3-state B output buffers are active and display the data present at the outputs of the A latches.

2. Features
s s s s s s s s s 5 V tolerant inputs/outputs for interfacing with 5 V logic Supply voltage range from 1.2 V to 3.6 V Complies with JEDEC standard JESD8-B/JESD36 CMOS low-power consumption Direct interface with TTL levels 8-bit octal transceiver with D-type latch Back-to-back registers for storage Separate controls for data flow in each direction Supports partial power-down applications; inputs/outputs are high-impedance when VCC = 0 V s ESD protection: x HBM EIA/JESD22-A114-B exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V. s Specified from -40 C to +85 C and -40 C to +125 C.