74LVC841A_3| Datasheet

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74LVC841A
10-bit transparent latch with 5 V tolerant inputs/outputs; 3-state
Rev. 03 -- 24 May 2004 Product data sheet

1. General description
The 74LVC841A is a high performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. In 3-state operation, outputs can handle 5 V. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment. The 74LVC841A is a 10-bit transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus-oriented applications. A latch enable (pin LE) input and an output enable (pin OE) input are common to all internal latches. The 74LVC841A consists of ten transparent latches with 3-state true outputs. When pin LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change each time its corresponding D-input changes. When pin LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of pin LE. When pin OE is LOW, the co
ntents of the ten latches are available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the pin OE input does not affect the state of the latches.

2. Features
s s s s s s s s 5 V tolerant inputs/outputs; for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V Inputs accept voltages up to 5.5 V CMOS low power consumption Direct interface with TTL levels Flow-through pin-out architecture Complies with JEDEC standard JESD8B/JESD36 ESD protection: x HBM EIA/JESD22-A114-B exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V. s Specified from -40 C to +85 C and -40 C to +125 C.