BUK9515_9615-100A_2| Datasheet

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Philips Semiconductors

Product specification

TrenchMOS transistor Logic level FET
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope available in TO220AB and SOT404 . Using 'trench' technology which features very low on-state resistance. It is intended for use in automotive and general purpose switching applications.

BUK9515-100A BUK9615-100A
QUICK REFERENCE DATA
SYMBOL VDS ID Ptot Tj RDS(ON) PARAMETER Drain-source voltage Drain current (DC) Total power dissipation Junction temperature Drain-source on-state resistance VGS = 5 V VGS = 10 V MAX. 100 75 230 175 15 14.4 UNIT V A W C m m

PINNING TO220AB & SOT404
PIN 1 2 3 DESCRIPTION gate drain
2

PIN CONFIGURATION
mb tab

SYMBOL
d

g
3 SOT404
1 2 3

source

tab/mb drain

TO220AB

LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDGR VGS VGSM ID ID IDM Ptot Tstg, Tj PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage Non-repetitive gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage & operating temperature CONDITIONS RGS = 20 k tp50uS Tmb = 25 C Tmb = 100 C Tmb = 25 C Tmb = 25 C MIN. - 55 MAX. 100 100 10 15 75 53 313 230 175 UNIT V V V V A A A W C

THERMAL RESISTANCES
SYMBOL Rth j-mb Rth j-a Rth j-a PARAMETER Thermal resistance junction to mounting base Thermal resistance junction to ambient(TO220AB) Thermal resistance junction to ambient(SOT404) CONDITIONS in free air Minimum footprint, FR4 board TYP. 60 50 MAX. 0.65 UNIT K/W K/W K/W

November 1999

Rev 1.000