BUK9608-55_2| Datasheet

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Philips Semiconductors

Product specification

TrenchMOSTM transistor Logic level FET
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope suitable for surface mounting Using 'trench' technology the device features very low on-state resistance and has integral zener diodes giving ESD protection up to 2kV. It is intended for use in automotive and general purpose switching applications.

BUK9608-55

QUICK REFERENCE DATA
SYMBOL VDS ID Ptot Tj RDS(ON) PARAMETER Drain-source voltage Drain current (DC) Total power dissipation Junction temperature Drain-source on-state resistance VGS = 5 V MAX. 55 75 187 175 8 UNIT V A W C m

PINNING - SOT404
PIN 1 2 3 mb gate drain source drain DESCRIPTION

PIN CONFIGURATION
mb

SYMBOL
d

g
2 1 3

LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDGR VGS ID ID IDM Ptot Tstg, Tj PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage & operating temperature CONDITIONS RGS = 20 k Tmb = 25 C Tmb = 100 C Tmb = 25 C Tmb = 25 C MIN. - 55 MAX. 55 55 10 75 65 240 187 175 UNIT V V V A A A W C

ESD LIMITING VALUE
SYMBOL VC PARAMETER Electrostatic discharge capacitor voltage CONDITIONS Human body model (100 pF, 1.5 k) MIN. MAX. 2 UNIT kV

THERMAL RESISTANCES
SYMBOL Rth j-mb Rth j-a PARAMETER Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS Minimum footprint,FR4 board TYP. 50 MAX. 0.8 UNIT K/W K/W

April 1998

Rev 1.000