GTL2018_1| Datasheet

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GTL2018
8-bit LVTTL to GTL transceiver
Rev. 01 -- 15 February 2007 Product data sheet

1. General description
The GTL2018 is an octal translating transceiver designed for 3.3 V LVTTL system interface with a GTL-/GTL/GTL+ bus. The direction pin (DIR) allows the part to function as either a GTL-to-LVTTL sampling receiver or as an LVTTL-to-GTL interface. The GTL2018 LVTTL inputs (only) are tolerant up to 5.5 V, allowing direct access to TTL or 5 V CMOS inputs.

2. Features
I Operates as an octal GTL-/GTL/GTL+ sampling receiver or as an LVTTL to GTL-/GTL/GTL+ driver I 3.0 V to 3.6 V operation with 5 V tolerant LVTTL input I GTL input and output 3.6 V tolerant I Vref adjustable from 0.5 V to 0.5VCC I Partial power-down permitted I Latch-up protection exceeds 500 mA per JESD78 I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-CC101 I Package offered: TSSOP24

3. Quick reference data
Table 1. Symbol Ci Cio Quick reference data Parameter input capacitance input/output capacitance Conditions control inputs; VI = 3.0 V or 0 V A port; VO = 3.0 V or 0 V B port; VO = VTT or 0 V GTL; Vref = 0.8 V; VTT = 1.2 V tPLH tPHL tPLH tPHL LOW-to-HIGH propagation delay HIGH-to-LOW propagation delay LOW-to-HIGH propagation delay HIGH-to-LOW propagation delay An to Bn; see Figure 3 An to Bn; see Figure 3 Bn to An; see Figure 4 Bn to An; see Figure 4 2.8 3.4 5.2 4.9 5 7 8 7 ns ns ns ns Min Typ 2 4.6 3.4 Max 2.5 6 4.3 Unit pF pF pF