PHB_PHD_PHP11N06LT_3| Datasheet

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Philips Semiconductors

Product specification

N-channel TrenchMOSTM transistor Logic level FET
FEATURES
'Trench' technology Low on-state resistance Fast switching Logic level compatible
g

PHP11N06LT, PHB11N06LT PHD11N06LT
QUICK REFERENCE DATA
d

SYMBOL

VDSS = 55 V ID = 10.5 A RDS(ON) 150 m (VGS = 5 V) RDS(ON) 130 m (VGS = 10 V)

GENERAL DESCRIPTION
N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using 'trench' technology. Applications: d.c. to d.c. converters switched mode power supplies The PHP11N06LT is supplied in the SOT78 (TO220AB) conventional leaded package. The PHB11N06LT is supplied in the SOT404 (D2PAK) surface mounting package. The PHD11N06LT is supplied in the SOT428 (DPAK) surface mounting package.

PINNING
PIN 1 2 3 tab DESCRIPTION gate drain 1 source

SOT78 (TO220AB)
tab

SOT404 (D2PAK)
tab

SOT428 (DPAK)
tab

2
1 23

drain

LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS VGSM ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Gate-source voltage Pulsed gate-source voltage Continuous drain current Pulsed drain current Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 C to 175 C Tj = 25 C to 175 C; RGS = 20 k Tj 150 C Tmb = 25 C Tmb = 100 C Tmb = 25 C Tmb = 25 C MIN. - 55 MAX. 55 55 15 20 10.3 7.3 41 33 175 UNIT V V V V A A A W C

1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages. August 1999 1 Rev 1.000