PHP80N06T_1| Datasheet

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Philips Semiconductors

Product specification

TrenchMOSTM transistor Standard level FET
GENERAL DESCRIPTION
N-channel enhancement mode standard level field-effect power transistor in a plastic envelope using 'trench' technology. The device features very low on-state resistance and has integral zener diodes giving ESD protection up to 2kV. It is intended for use in DC-DC converters and general purpose switching applications.

PHP80N06T

QUICK REFERENCE DATA
SYMBOL VDS ID Ptot Tj RDS(ON) PARAMETER Drain-source voltage Drain current (DC)1 Total power dissipation Junction temperature Drain-source on-state resistance VGS = 10 V MAX. 55 75 178 175 14 UNIT V A W C m

PINNING - TO220AB
PIN 1 2 3 tab gate drain source drain DESCRIPTION

PIN CONFIGURATION
tab

SYMBOL
d

g s

1 23

LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDGR VGS ID ID IDM Ptot Tstg, Tj PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC)1 Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage & operating temperature CONDITIONS RGS = 20 k Tmb = 25 C Tmb = 100 C Tmb = 25 C Tmb = 25 C MIN. - 55 MAX. 55 55 20 75 56 240 178 175 UNIT V V V A A A W C

ESD LIMITING VALUE
SYMBOL VC PARAMETER Electrostatic discharge capacitor voltage, all pins CONDITIONS Human body model (100 pF, 1.5 k) MIN. MAX. 2 UNIT kV

1 Current limited by package to 75A from a theoretical value of 80A. December 1997 1 Rev 1.100