NB6L14M-D| Datasheet

NB6L14M-D| Datasheet

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NB6L14M 2.5 V/3.3 V3.0 GHz Differential 1:4 CML Fanout Buffer
Multi-Level Inputs with Internal Termination
http://onsemi.com Description

The NB6L14M is a 3.0 GHz differential 1:4 CML clock or data fanout buffer. The differential inputs incorporate internal 50 W termination resistors that are accessed through the VT pin. This feature allows the NB6L14M to accept various logic standards, such as LVPECL, CML, or LVDS logic levels. The 16 mA differential CML outputs provide matching internal 50 W terminations and produce 400 mV output swings when externally terminated with a 50 W resistor to VCC. The VREFAC reference output can be used to rebias capacitor-coupled differential or single-ended input signals. The 1:4 fanout design was optimized for low output skew applications. The NB6L14M is a member of the ECLinPS MAXTM family of high performance clock and data products.
Features

MARKING DIAGRAM*
16 1 QFN-16 MN SUFFIX CASE 485G NB6L 14M ALYWG G

A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D.

Input Clock Frequency > 3.0 GHz Input Data Rate > 2.5 Gb/s < 20 ps Within Device Output Skew 350 ps Typical Propagation Delay 90 ps Typical Rise and Fall Times Differential CML Outputs, 340 mV Amplitude, Typical CML Mode Operating Range: VCC = 2.375 V to 3.63 V with GND = 0 V Internal Input and Output Termination Resistors, 50 W VREFAC Reference Output Voltage -40 C to +85 C Ambient Operating Temperature Available in 3 mm x 3 mm 16 Pin QFN These are Pb-Free Devices

Q0 Q0

Q1 IN VT IN Q2 Q2 Q1

EN

D

Q

Q3 VREFAC Q3

Figure 1. Simplified Logic Diagram

ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet.

Semiconductor Components Industries, LLC, 2008

1

April, 2008 - Rev. 3

Publication Order Number: NB6L14M/D


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