NLAST4051-D| Datasheet

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NLAST4051 Analog Multiplexer/ Demultiplexer
TTL Compatible, Single-Pole, 8-Position Plus Common Off
http://onsemi.com

The NLAST4051 is an improved version of the MC14051 and MC74HC4051 fabricated in sub-micron Silicon Gate CMOS technology for lower RDS(on) resistance and improved linearity with low current. This device may be operated either with a single supply or dual supply up to 3 V to pass a 6 VPP signal without coupling capacitors. When operating in single supply mode, it is only necessary to tie VEE, pin 7 to ground. For dual supply operation, VEE is tied to a negative voltage, not to exceed maximum ratings. Translation is provided in the device, the Address and Inhibit are standard TTL level compatible. For CMOS compatibility see NLAS4051. Pin for pin compatible with all industry standard versions of `4051.'
Features

MARKING DIAGRAMS
16 SOIC-16 D SUFFIX CASE 751B 1 1

NLAST4051 AWLYWW

16 TSSOP-16 DT SUFFIX CASE 948F 1 1 AST 4051 ALYWG G

Improved RDS(on) Specifications Pin for Pin Replacement for MAX4051 and MAX4051A
- One Half the Resistance Operating at 5.0 V Single or Dual Supply Operation - Single 3.0 - 5.0 V Operation, or Dual 3 V Operation - With VCC of 3.0 to 3.3 V, Device Can Interface with 1.8 V Logic, - No Translators Needed - Address and Inhibit Logic are Over-Voltage Tolerant and May Be - Driven Up +6 V Regardless of VCC Address and Inhibit Pins Standard TTL Compatible - Greatly Improved Noise Margin Over MAX4051 and MAX4051A - True TTL Compatibility VIL = 0.8 V, VIH = 2.0 V Improved Linearity Over Standard HC4051 Devices Popular SOIC, and Space Saving TSSOP, and QSOP 16 Pin Packages Pb-Free Packages are Available*
VCC 16 NO2 15 NO4 14 NO0 13 NO6 ADDC ADDB ADDA 12 11 10 9

16 QSOP-16 QS SUFFIX CASE 492 1 1 NLAST 4051 ALYW

A = Assembly Location WL, L = Wafer Lot Y = Year WW, W = Work Week G = Pb-Free Package (Note: Microdot may be in either location)

ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet.

1 NO1

4 NO7

5 NO5

8 GND

NO3 COM

Inhibit VEE

Figure 1. Pin Connection (Top View)
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
Semiconductor Components Industries, LLC, 2006

April, 2006 - Rev. 4

Publication Order Number: NLAST4051/D