rej03d0608_hd74hc292_294ds| Datasheet

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HD74HC292/HD74HC294
Programmable Frequency Divider/Digital Timer
REJ03D0608 0200 (Previous ADE-205-486) Rev.2.00 Jan 31, 2006

Description
This device divides the incoming clock frequency by a number (a power of 2) that is preset by the Programming inputs. It has two Clock inputs, either of which may be used as a clock inhibit. The device also has an active-low Reset, which initializes the internal flip-flop states. Test Point outputs (TP1, TP2, TP3) are provided with HD74HC292 to facilitate incoming inspections. Test Point output is provided with HD74HC294 to facilitate incoming inspections.

Features
High Speed Operation: tpd (Clock to Q) = 16 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 uA max Low Quiescent Supply Current: ICC (static) = 4 uA max (Ta = 25 C) Ordering Information
Part Name HD74HC292P HD74HC294FPEL Package Type DILP-16 pin SOP-16 pin (JEITA) Package Code (Previous Code) PRDP0016AE-B (DP-16FV) Package Abbreviation P -- EL (2,000 pcs/reel) Taping Abbreviation (Quantity)

PRSP0016DH-B FP (FP-16DAV) Note: Please consult the sales office for the above package availability.

Function Table
CLR L H H H H high level low level CLK1 X L H X CLK2 X L X H Q Output Mode Cleared to L Count Count Inhibit Inhibit

H : L :

Rev.2.00 Jan 31, 2006 page 1 of 9

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