rej03f0176_m66310pds| Datasheet

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M66310P/FP

Logic Diagram
Parallel data outputs QA
1

QB
2

QC
24

QD
23

QE
22

QF
21

QG
20

QH
19

QI
18

QJ
17

QK
16

QL
15

QM
14

QN
13

QO
11

QP
12

Serial data output SQP VCC
10 3

0 CK D R

0 CK D R

0 CK D R

0 CK D R

0 CK D R

0 CK D R

0 CK D R

0 CK D R

0 CK D R

0 CK D R

0 CK D R

0 CK D R

0 CK D R

0 CK D R

0 CK D R

0 CK D R

1 CK D R

1 CK D R

1 CK D R

1 CK D R

1 CK D R

1 CK D R

1 CK D R

1 CK D R

1 CK D R

1 CK D R

1 CK D R

1 CK D R

1 CK D R

1 CK D R

1 CK D R

1 CK D R

5

4

8

7

6

9

A OE Enable Serial input data input

VCC
Parallel data output

VCC

Serial data output

CKS CKL GND R Shift Direct Latch clock reset clock input input input

Output format

Pin Arrangement
M66310P/FP

Parallel data outputs

QA 1 QB 2 VCC
3

QA QB

QC QD QE

24 QC 23 QD 22 QE 21 QF 20 QG 19 QH 18 QI 17 QJ 16 QK 15 QL 14 QM 13 QN

Serial data input Enable input

A 4 OE 5

A OE CKL R CKS

QF QG QH QI QJ QK

Latch clock input CKL 6 Direct reset input R 7

Parallel data outputs

Shift clock input CKS 8 GND
9

Serial data output SQP 10 Parallel data outputs QO 11 QP 12

SQP QO QP

QL QM QN

(Top view) Outline: PRDP0024AA-A (24P4D) (24P2N-B)

REJ03F0176-0201 Rev.2.01 Mar 31, 2008 Page 2 of 9

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