74AC10| Datasheet

74AC10, 74AC10MTR, 74AC10TTR

Datasheet preview, take a look at Datasheets before downloading (Data Sheet is available on manufacturer site)

74AC10
TRIPLE 3-INPUT NAND GATE
s s

HIGH SPEED: tPD = 4ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 2uA(MAX.) at TA=25 C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) 50 TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 10 IMPROVED LATCH-UP IMMUNITY

DIP

SOP

TSSOP

ORDER CODES
PACKAGE DIP SOP TSSOP TUBE 74AC10B 74AC10M T&R 74AC10MTR 74AC10TTR

DESCRIPTION The 74AC10 is an advanced high-speed CMOS TRIPLE 3-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology.

The internal circuit is composed of 3 stages including buffer output, which enables high noise immunity and stable output. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

April 2001

1/8