74AC125| Datasheet

74AC125, 74AC125MTR, 74AC125TTR

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74AC125
QUAD BUS BUFFERS (3-STATE)
s s

HIGH SPEED: tPD = 4ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4uA(MAX.) at TA=25 C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) 50 TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 125 IMPROVED LATCH-UP IMMUNITY

DIP

SOP

TSSOP

ORDER CODES
PACKAGE DIP SOP TSSOP TUBE 74AC125B 74AC125M T&R 74AC125MTR 74AC125TTR

DESCRIPTION The 74AC125 is an advanced high-speed CMOS QUAD BUS BUFFER fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.

The device requires the 3-STATE control input G to be set high to place the output go in to the high impedance state. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

July 2001

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