74AC373| Datasheet

74AC373, 74AC373MTR, 74AC373TTR

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74AC373
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS (NON INVERTED)
s s

HIGH SPEED: tPD = 5ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4uA(MAX.) at TA=25 C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) 50 TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373 IMPROVED LATCH-UP IMMUNITY

DIP

SOP

TSSOP

ORDER CODES
PACKAGE DIP SOP TSSOP TUBE 74AC373B 74AC373M T&R 74AC373MTR 74AC373TTR

DESCRIPTION The 74AC373 is a high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE). While the LE inputs is held at a high level, the Q outputs will follow the data input. When the LE is taken low, the Q outputs will be latched at the PIN CONNECTION AND IEC LOGIC SYMBOLS

logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level); while OE is in high level the outputs will be in a high impedance state. This device is designed to interface directly High Speed CMOS systems with TTL and NMOS components. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

April 2001

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