74ACT257| Datasheet

74ACT257, 74ACT257MTR, 74ACT257TTR

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74ACT257
QUAD 2 CHANNEL MULTIPLEXER (3-STATE)
s s

HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 uA(MAX.) at TA=25 C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.), V IL = 0.8V (MAX.) 50 TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 257 IMPROVED LATCH-UP IMMUNITY

DIP

SOP

TSSOP

ORDER CODES
PACKAGE DIP SOP TSSOP TUBE 74ACT257B 74ACT257M T&R 74ACT257MTR 74ACT257TTR

DESCRIPTION The 74ACT257 is an advanced high-speed CMOS QUAD 2-CHANNEL MULTIPLEXER (3-STATE) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology. It is composed of an independent 2-channel multiplexer with common SELECT and ENABLE (OE)inputs. It is a non-inverting multiplexer. When the ENABLE input is held HIGH, the outputs are forced to a high impedance state. When the

SELECT input is held LOW, "A" data is selected; when SELECT input is held HIGH, "B" data is selected. The device is designed to interface directly High Speed CMOS systems with TTL, NMOS and CMOS output voltage levels. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

April 2001

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