74ACT280| Datasheet

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74ACT280
9 BIT PARITY GENERATOR/CHECKER
s s

HIGH SPEED: tPD = 7ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4uA(MAX.) at TA=25 C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.), V IL = 0.8V (MAX.) 50 TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 280 IMPROVED LATCH-UP IMMUNITY

DIP

SOP

TSSOP

ORDER CODES
PACKAGE DIP SOP TSSOP TUBE 74ACT280B 74ACT280M T&R 74ACT280MTR 74ACT280TTR

DESCRIPTION The 74ACT280 is an advanced high-speed CMOS 9 BIT PARITY GENERATOR CHECKER fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology. It is composed of nine data inputs (A to I) and odd/ even parity outputs (ODD and EVEN). The nine data inputs control the output conditions. When the number of high level input is odd, ODD output is kept high and EVEN output low. PIN CONNECTION AND IEC LOGIC SYMBOLS

Conservely, when the output is even, EVEN output is kept high and ODD low. The IC generates either odd or even parity making it flexible application. The word-length capability is easly expanded by cascading. The device is designed to interface directly High Speed CMOS systems with TTL, NMOS and CMOS output voltage levels. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

April 2001

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