74LVC245A| Datasheet

74LVC245A, 74LVC245AMTR, 74LVC245ATTR

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74LVC245A
LOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER (NOT INVERTED) HIGH PERFORMANCE
s s s

s s

5V TOLERANT INPUTS HIGH SPEED: tPD = 6.3ns (MAX.) at VCC = 3V POWER DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 3V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 1.65V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 245 LATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17) ESD PERFORMANCE: HBM > 2000V (MIL STD 883 method 3015); MM > 200V

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TSSOP

Table 1: Order Codes
PACKAGE SOP TSSOP T&R 74LVC245AMTR 74LVC245ATTR

DESCRIPTION The 74LVC245A is a low voltage CMOS OCTAL BUS TRANSCEIVER (3-STATE) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for 1.65 to 3.6 VCC operations and low power and low noise applications. This IC is intended for two-way asynchronous communication between data buses and the Figure 1: Pin Connection And IEC Logic Symbols

direction of data transmission is determined by DIR input. The enable input G can be used to disable the device so that the buses are effectively isolated. It has more speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption. All inputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. All floating bus terminals during High Z State must be held HIGH or LOW.

July 2004
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Rev. 4

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