74LVCZ161284A| Datasheet

74LVCZ161284A, 74LVCZ161284ATTR

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74LVCZ161284A
LOW VOLTAGE HIGH SPEED IEEE1284 TRANSCEIVER WITH ERROR-FREE POWER-UP
I I

HIGH SPEED: tPD = 9ns (MAX.) at VCC = 3V LOW POWER DISSIPATION: ICC=20uA (MAX) at VCC=3.6V TA=85 C TTL COMPATIBLE INPUTS VIH=2V (MIN) VIL=0.8(MAX) OPERATING VOLTAGE RANGE: VCC(OPR) = 3.0V to 3.6V A PORT HAVE STANDARD 4mA TOTEM POLE OUTPUT B PORT HIGH DRIVE SOURCE/SINK CAPABILITY OF 14mA AUTO POWER-UP FEATURE TO PREVENT PRINTER ERRORS SUPPORT IEEE STD 1284-I (LEVEL 1 TYPE) AND IEEE STD 1284-II (LEVEL 2 TYPE) FOR BIDIRECTIONAL PARALLEL COMMUNICATIONS BETWEEN PERSONAL COMPUTER ANT PRINTING PERIPHERALS TRANSLATION CAPABILITY ALLOW OUTPUTS ON CABLE SIDE TO INTERFACE WITH 5V SIGNAL PULL-UP RESISTOR INTEGRATED ON ALL OPEN-DRAIN OUTPUT ELIMINATE THE NEED FOR DISCRETE RESISTOR REPLACE THE FUNCTION OF TWO 74LVC1284 DEVICES

TSSOP

ORDER CODES
PACKAGE TSSOP TUBE T&R 74LVCZ161284ATTR

PIN CONNECTION

DESCRIPTION The 74LVCZ161284A contains eight high speed non inverting bidirectional buffers and eleven control/status non-inverting buffers with open drain outputs fabricated in silicon gate C2MOS technology. It's intended to provide a standard signaling method for a bi-direction parallel peripheral in an Extended Capabilities Port Mode (ECP). The HD (Active HIGH) input pin enables the Cable port to switch from Open Drain to a high drive totem pole output, capable of sourcing 14mA on all thirteen buffer and 84mA on PERI LOGIC OUTPUT buffer. The DIR input determines the direction of data flow on the bidirectional buffers. DIR (Active HIGH) enables data flow from A port to B port. DIR (Active LOW) enables data flow from B port to A port. The Y output (Y9-Y13) stay in the high state after power-on until an associated input A9-A13) goes high. When an associated input goes high, all Y outputs are active, and non
July 2005 1/12