74LVQ273| Datasheet

74LVQ273, 74LVQ273MTR, 74LVQ273TTR

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74LVQ273
OCTAL D-TYPE FLIP FLOP WITH CLEAR
s

s s

HIGH SPEED: fMAX = 150 MHz (TYP.) at VCC = 3.3 V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 4 uA (MAX.) at TA=25 C LOW NOISE: VOLP = 0.4V (TYP.) at VCC = 3.3V 75 TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 12mA (MIN) at VCC = 3.0 V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 273 IMPROVED LATCH-UP IMMUNITY

SOP

TSSOP

Table 1: Order Codes
PACKAGE SOP TSSOP T&R 74LVQ273MTR 74LVQ273TTR

DESCRIPTION The 74LVQ273 is a low voltage CMOS OCTAL D-TYPE FLIP FLOP WITH CLEAR fabricated with sub-micron silicon gate and double-layer metal

wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications. Information signals applied to D inputs are transferred to the Q outputs on the positive going edge of the CLOCK pulse. When the CLEAR input is held low, the Q outputs are held low independently of the other inputs. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

Figure 1: Pin Connection And IEC Logic Symbols

July 2004

Rev. 5

1/13