74LVX132| Datasheet

74LVX132, 74LVX132MTR, 74LVX132TTR

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74LVX132
LOW VOLTAGE CMOS QUAD 2-INPUT SCHMITT NAND GATE WITH 5V TOLERANT INPUTS
s

s s

HIGH SPEED: tPD = 5.9ns (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS LOW POWER DISSIPATION: ICC = 2 uA (MAX.) at TA=25 C TYPICAL HYSTERESIS: 0.7V at VCC = 3.3V LOW NOISE: VOLP = 0.3V (TYP.) at VCC = 3.3V SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 132 IMPROVED LATCH-UP IMMUNITY POWER DOWN PROTECTION ON INPUTS

SOP

TSSOP

Table 1: Order Codes
PACKAGE SOP TSSOP T&R 74LVX132MTR 74LVX132TTR

DESCRIPTION The 74LVX132 is a low voltage CMOS QUAD 2-INPUT SCHMITT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power, battery operated and low noise 3.3V applications. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. Figure 1: Pin Connection And IEC Logic Symbols

This device can be used to interface 5V to 3V system. It combines high speed performance with the true CMOS low power consumption. Pin configuration and function are the same as those of the 74LVX00 but the 74LVX132 has hysteresis. This together with its schmitt trigger function allows it to be used on line receivers with slow rise/fall input signals. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

August 2004

Rev. 3

1/11