74LVX139| Datasheet

74LVX139, 74LVX139MTR, 74LVX139TTR

Datasheet preview, take a look at Datasheets before downloading (Data Sheet is available on manufacturer site)

74LVX139
LOW VOLTAGE CMOS DUAL 2 TO 4 DECODER/DEMULTIPLEXER
s

s s

HIGH SPEED : tPD = 6.0ns (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS INPUT VOLTAGE LEVEL : VIL=0.8V, VIH=2V at VCC=3V LOW POWER DISSIPATION: ICC = 2 uA (MAX.) at TA=25 C LOW NOISE: VOLP = 0.3V (TYP.) at VCC = 3.3V SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 139 IMPROVED LATCH-UP IMMUNITY POWER DOWN PROTECTION ON INPUTS

SOP

TSSOP

Table 1: Order Codes
PACKAGE SOP TSSOP T&R 74LVX139MTR 74LVX139TTR

DESCRIPTION The 74LVX139 is a low voltage CMOS DUAL 2 TO 4 DECODER/DEMULTIPLEXER fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power, battery operated and low noise 3.3V applications. Figure 1: Pin Connection And IEC Logic Symbols

The active low enable input can be used for gating or as a data input for demultiplexing applications. While the enable input is held high, all four outputs are high independently of the other inputs. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V system. It combines high speed performance with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

August 2004

Rev. 2

1/12