74LVX16373| Datasheet

74LVX16373, 74LVX16373TTR

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74LVX16373
LOW VOLTAGE CMOS 16-BIT D-TYPE LATCH (3-STATE) WITH 5V TOLERANT INPUTS
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HIGH SPEED : tPD = 5.4 ns (MAX.) at VCC = 3V 5V TOLERANT INPUTS POWER DOWN PROTECTION ON INPUTS INPUT VOLTAGE LEVEL: VIL = 0.8V, VIH = 2V at VCC =3V LOW POWER DISSIPATION: ICC = 4 uA (MAX.) at TA=25 C LOW NOISE: VOLP = 0.3V (TYP.) at VCC =3.3V SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4 mA (MIN) at VCC =3V BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 16373 IMPROVED LATCH-UP IMMUNITY

TSSOP

ORDER CODES
PACKAGE TSSOP TUBE T&R 74LVX16373TTR

PIN CONNECTION

DESCRIPTION The 74LVX16373 is a low voltage CMOS 16 BIT D-TYPE LATCH with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power, battery operated and low noise 3.3V applications. These 16 bit D-TYPE latches are byte controlled by two latch enable inputs (nLE) and two output enable inputs(OE). While the nLE input is held at a high level, the nQ outputs will follow the data input precisely. When the nLE is taken LOW, the nQ outputs will be latched precisely at the logic level of D input data. While the (nOE) input is low, the nQ outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. It combines high speed performance with the true CMOS low power consumption. All inputs and out
puts are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
February 2003 1/10