74LVX74| Datasheet

74LVX74, 74LVX74MTR, 74LVX74TTR

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74LVX74
LOW VOLTAGE CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR (5V TOLERANT INPUTS)
s

s s

HIGH SPEED: fMAX = 145MHz (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS INPUT VOLTAGE LEVEL: VIL=0.8V, VIH=2V AT VCC=3V LOW POWER DISSIPATION: ICC = 2 uA (MAX.) at TA=25 C LOW NOISE: VOLP = 0.3V (TYP.) at VCC = 3.3V SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 74 IMPROVED LATCH-UP IMMUNITY POWER DOWN PROTECTION ON INPUTS

SOP

TSSOP

Table 1: Order Codes
PACKAGE SOP TSSOP T&R 74LVX74MTR 74LVX74TTR

DESCRIPTION The 74LVX74 is a low voltage CMOS DUAL D-TYPE FLIP-FLOP WITH PRESET AND CLEAR NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power, battery operated and low noise 3.3V applications. Figure 1: Pin Connection And IEC Logic Symbols

A signal on the D INPUT is transferred to the Q OUTPUT during the positive going transition of the clock pulse. CLR and PR are independent of the clock and accomplished by a low setting on the appropriate input. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V system. It combines high speed performance with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

August 2004

Rev. 3

1/13