74LX1G132| Datasheet

74LX1G132, 74LX1G132CTR, 74LX1G132STR

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74LX1G132
SINGLE 2-INPUT SCHMITT NAND GATE
s s s

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5V TOLERANT INPUTS HIGH SPEED: tPD = 5.5ns (MAX.) at VCC = 3V LOW POWER DISSIPATION: ICC = 1uA (MAX.) at TA = 25 C TYPICAL HYSTERESIS: Vh=1V at VCC=4.5V POWER DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 3V BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 1.65V to 5.5V (1.2V Data Retention) IMPROVED LATCH-UP IMMUNITY

SOT23-5L

SOT323-5L

ORDER CODES
PACKAGE SOT23-5L SOT323-5L T&R 74LX1G132STR 74LX1G132CTR

DESCRIPTION The 74LX1G132 is a low voltage CMOS SINGLE 2-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. The internal circuit is composed of 3 stages including buffer output, which provide high noise immunity and stable output.

Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. This together with its schmitt trigger function allows it to be used on line receivers with slow rise/fall input signals. All inputs and outputs are equipped with protection circuits against static discharge.

PIN CONNECTION AND IEC LOGIC SYMBOLS

April 2004

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