74VCXH1632245| Datasheet

74VCXH1632245, 74VCXH1632245LBR, 74VCXH1632245TBR, 74VCXH1632245TTR

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74VCXH1632245
16-BIT DUAL SUPPLY BUS TRANSCEIVER LEVEL TRANSLATOR WITH A SIDE SERIES RESISTOR
s

s s

HIGH SPEED: tPD = 4.4ns (MAX.) at TA=85 C VCCA = 3.0V VCCB = 2.3V LOW POWER DISSIPATION: ICCA = ICCB = 20uA(MAX.) at TA=85 C SYMMETRICAL OUTPUT IMPEDANCE: |IOHA| = IOLA = 8mA MIN at VCCA = 3.0V; VCCB = 1.65V or 2.3V |IOHB| = IOLB = 6mA (MIN at VCCA = 2.3V or 3.0V; VCCB = 1.65V) BALANCED PROPAGATION DELAYS: tPLH tPHL POWER DOWN PROTECTION ON INPUTS AND OUTPUTS SERIES RESISTOR ON A SIDE OPERATING VOLTAGE RANGE: VCCA(OPR) = 2.3V to 3.6V (1.2V Data Retention) VCCB(OPR) = 1.65V to2.7V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 16245 BUS HOLD PROVIDED ON DATA INPUT BOTH SIDE LATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17) ESD PERFORMANCE: HBM > 2000V (MIL STD 883 method 3015); MM > 200V

TSSOP

TFBGA

uTFBGA

ORDER CODES
PACKAGE TSSOP48 TFBGA54 uTFBGA42 T&R 74VCXH1632245TTR 74VCXH1632245LBR 74VCXH1632245TBR

bus terminals during High Z State don't need external pull-up or pull-down resistor.

LOGIC DIAGRAM

DESCRIPTION The 74VCXH1632245 is a dual supply low voltage CMOS 16-BIT BUS TRANSCEIVER fabricated with sub-micron silicon gate and five-layer metal wiring C2MOS technology. Designed for use as an interface between a 3.3V bus and a 2.5V or 1.8V bus in a mixed 3.3V/1.8V,3.3V/2.5V and 2.5V/ 1.8V supply systems, it achieves high speed operation while maintaining the CMOS low power dissipation. This IC is intended for two-way asynchronous communication between data buses and the direction of data transmission is determined by nDIR inputs. The enable inputs nG can be used to disable the device so that the buses are effectively isolated. The A-port interfaces with the 3V bus, the B-port with the 2.5V and 1.8V bus. All inputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. All floating
June 2004

n = 1, 2

Rev. 1

1/17