74VHC16373| Datasheet

74VHC16373, 74VHC16373TTR

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74VHC16373
16-BIT D-TYPE LATCH WITH 3-STATE OUTPUTS NON INVERTING
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HIGH SPEED: tPD = 5.0 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 uA (MAX.) at TA=25 C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 16373 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP = 0.9V (MAX.)

TSSOP

ORDER CODES
PACKAGE TSSOP TUBE T&R 74VHC16373TTR

PIN CONNECTION

DESCRIPTION The 74VHC16373 is an advanced high-speed CMOS 16 BIT D-TYPE LATCH with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 16 bit D-TYPE latches are byte controlled by two latch enable inputs (nLE) and two output enable inputs(nOE). While the nLE input is held at a high level, the nQ outputs will follow the data (D) inputs. When the nLE is taken LOW, the nQ outputs will be latched at the logic level of D data inputs. When the (nOE) input is low, the nQ outputs will be in a normal logic state (high or low logic level); when nOE is at high level ,the outputs will be in a high impedance state. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

February 2003

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