74VHC238| Datasheet

74VHC238, 74VHC238MTR, 74VHC238TTR

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74VHC238
3 TO 8 LINE DECODER
s s

s s

HIGH SPEED: tPD = 5.5 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 uA (MAX.) at TA=25 C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 238 IMPROVED LATCH-UP IMMUNITY

SOP

TSSOP

Table 1: Order Codes
PACKAGE SOP TSSOP T&R 74VHC238MTR 74VHC238TTR

DESCRIPTION The 74VHC238 is an advanced high-speed CMOS 3 TO 8 LINE DECODER fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. If the device is enabled, 3 binary select inputs (A, B, and C) determine which one of the outputs will go high. If enable input G1 is held low or either G2A or G2B is held high, decoding function is inhibited and all the 8 outputs go to low.

Tree enable inputs are provided to ease cascade connection and application of address decoders for memory systems. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

Figure 1: Pin Connection And IEC Logic Symbols

November 2004

Rev. 4

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