74VHC574| Datasheet

74VHC574, 74VHC574MTR, 74VHC574TTR

Datasheet preview, take a look at Datasheets before downloading (Data Sheet is available on manufacturer site)

74VHC574
OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUTS NON INVERTING
s s s

s s

HIGH SPEED: fMAX = 180 MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 uA (MAX.) at TA=25 C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 574 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP = 0.9V (MAX.)

SOP

TSSOP

Table 1: Order Codes
PACKAGE SOP TSSOP T&R 74VHC574MTR 74VHC574TTR

DESCRIPTION The 74VHC574 is an advanced high-speed CMOS OCTAL D-TYPE FLIP FLOP with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 8 bit D-Type flip-flop is controlled by a clock input (CK) and an output enable input (OE). On the positive transition of the clock, the Q outputs will be set to the logic states that were setup at the D inputs. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and Figure 1: Pin Connection And IEC Logic Symbols

while high level the outputs will be in a high impedance state. The Output control does not affect the internal operation of flip flop; that is, the old data can be retained or the new data can be entered even while the outputs are off. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

November 2004

Rev. 4

1/14