74VHC594| Datasheet

74VHC594, 74VHC594MTR, 74VHC594TTR

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74VHC594
8 BIT SHIFT REGISTER WITH OUTPUT REGISTER
s s

s s

HIGH SPEED: tPD = 4.2ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 uA (MAX.) at TA=25 C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 594 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP = 0.8V (MAX.)

SOP

TSSOP

Table 1: Order Codes
PACKAGE SOP TSSOP T&R M74VHC594RMTR M74VHC594TTR

DESCRIPTION The 74VHC594 is an high speed CMOS 8-BIT SHIFT REGISTERS fabricated with sub-micron silicon gate C2MOS technology. This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Separate clocks and direct overriding clear (SCLR, RCLR) are provided for both the shift register and the storage register.

A serial (QH') output is provided for cascading purposes. Both the shift register and storage register use positive-edge triggered clocks. If the clocks are connected together, the shift register state will always be one clock pulse ahead of the storage register. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

Figure 1: Pin Connection And IEC Logic Symbols

November 2004

Rev. 5

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