74VHC74| Datasheet

74VHC74, 74VHC74MTR, 74VHC74TTR

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74VHC74
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
s

s s

HIGH SPEED: fMAX = 170 MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 2 uA (MAX.) at TA=25 C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 74 IMPROVED LATCH-UP IMMUNITY

SOP

TSSOP

Table 1: Order Codes
PACKAGE SOP TSSOP T&R 74VHC74MTR 74VHC74TTR

DESCRIPTION The 74VHC74 is an advanced high-speed CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. A signal on the D INPUT is transferred to the Q OUTPUTS during the positive going transition of the clock pulse.

CLR and PR are independent of the clock and accomplished by a low setting on the appropriate input. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

Figure 1: Pin Connection And IEC Logic Symbols

November 2004

Rev. 4

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