74VHC86| Datasheet

74VHC86, 74VHC86MTR, 74VHC86TTR

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74VHC86
QUAD EXCLUSIVE OR GATE
s s

s s

HIGH SPEED: tPD = 4.8 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 2 uA (MAX.) at TA=25 C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 86 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP = 0.8V (MAX.)

SOP

TSSOP

Table 1: Order Codes
PACKAGE SOP TSSOP T&R 74VHC86MTR 74VHC86TTR

DESCRIPTION The 74VHC86 is an advanced high-speed CMOS QUAD EXCLUSIVE OR GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.

Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

Figure 1: Pin Connection And IEC Logic Symbols

November 2004

Rev. 5

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