74VHCT138A| Datasheet

74VHCT138A, 74VHCT138AMTR, 74VHCT138ATTR

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74VHCT138A
3 TO 8 LINE DECODER (INVERTING)
s s

s s

HIGH SPEED: tPD = 7.6 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 uA (MAX.) at TA=25 C COMPATIBLE WITH TTL OUTPUTS: VIH = 2V (MIN.), VIL = 0.8V (MAX) POWER DOWN PROTECTION ON INPUTS & OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 138 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP = 0.8V (MAX.)

SOP

TSSOP

Table 1: Order Codes
PACKAGE SOP TSSOP T&R 74VHCT138AMTR 74VHCT138ATTR

DESCRIPTION The 74VHCT138A is an advanced high-speed CMOS 3 TO 8 LINE DECODER (INVERTING) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. If the device is enabled, 3 binary select inputs (A, B, and C) determine which one of the outputs will go low. When enable input G1 is held low or either G2A or G2B is held high, the decoding function is inhibited and all the 8 outputs go to high. Figure 1: Pin Connection And IEC Logic Symbols

The three enable inputs are provided to ease cascade connection and application of address decoders for memory systems. Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V since all inputs are equipped with TTL threshold. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

December 2004

Rev. 3

1/12