74VHCT139A| Datasheet

74VHCT139A, 74VHCT139AMTR, 74VHCT139ATTR

Datasheet preview, take a look at Datasheets before downloading (Data Sheet is available on manufacturer site)

74VHCT139A
DUAL 2 TO 4 DECODER/DEMULTIPLEXER
s s

HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 2 uA (MAX.) at TA=25 C COMPATIBLE WITH TTL OUTPUTS: VIH = 2V (MIN.), VIL = 0.8V (MAX) POWER DOWN PROTECTION ON INPUTS & OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 139 IMPROVED LATCH-UP IMMUNITY

SOP

TSSOP

Table 1: Order Codes
PACKAGE SOP TSSOP T&R 74VHCT139AMTR 74VHCT139ATTR

DESCRIPTION The 74VHCT139A is an advanced high-speed CMOS DUAL 2 TO 4 LINE DECODER/ DEMULTIPLEXER fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. The active low enable input can be used for gating or as a data input for demultiplexing applications. When the enable input is held high, all four outputs are high independently of the other inputs.

Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V since all inputs are equipped with TTL threshold. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

Figure 1: Pin Connection And IEC Logic Symbols

December 2004

Rev. 3

1/12