74VHCT238A| Datasheet

74VHCT238A, 74VHCT238AMTR, 74VHCT238ATTR

Datasheet preview, take a look at Datasheets before downloading (Data Sheet is available on manufacturer site)

74VHCT238A
3 TO 8 LINE DECODER
s s

HIGH SPEED: tPD = 5.5 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 uA (MAX.) at TA=25 C COMPATIBLE WITH TTL OUTPUTS: VIH = 2V (MIN.), VIL = 0.8V (MAX) POWER DOWN PROTECTION ON INPUTS & OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 238 IMPROVED LATCH-UP IMMUNITY

SOP

TSSOP

Table 1: Order Codes
PACKAGE SOP TSSOP T&R 74VHCT238AMTR 74VHCT238ATTR

DESCRIPTION The 74VHCT238A is an advanced high-speed CMOS 3 TO 8 LINE DECODER fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. When the device is enabled, 3 binary select inputs (A, B, and C) determine which one of the outputs will go high. If enable input G1 is held low or either G2A or G2B is held high, decoding function is inhibited and all the 8 outputs go to low.

The three enable inputs are provided to ease cascade connection and application of address decoders for memory systems. Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V since all inputs are equipped with TTL threshold. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

Figure 1: Pin Connection And IEC Logic Symbols

December 2004

Rev. 3

1/12