DSM2150F5V, DSM2150F5V-12T6
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DSM2150F5V
DSM (Digital Signal Processor System Memory) for Analog Devices DSPs (3.3V Supply)
FEATURES SUMMARY
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Glueless Connection to DSP Easily add memory, logic, and I/O to the External Port of ADSP-218x, 219x, 2106x, 2116x, 2153x, and TS101 families of DSPs from Analog Devices, Inc. Dual Flash Memories Two independent Flash memory arrays for storing DSP code and data Capable of read-while-write concurrent Flash memory operation Device can be configured as 8-bit or 16-bit Built-in programmable address decoding logic allows mapping individual sectors of each Flash array to any address boundary Each Flash sector can be write protected 512 KByte Main Flash memory Ample storage for boot loading DSP code/ data upon reset and subsequent code swaps Large capacity for storing tables and constants or for data recording 32 KByte Secondary Flash memory Smaller sector size ideal for storing calibration and configuration constants. Eliminate external serial EEPROM. Optionally bypass internal DSP boot ROM during start-up and execute code directly from Secondary Flash. Use for custom start-up code and In-Appli
cation Programming (IAP). Up to 40 Multifunction I/O Pins Increase total DSP system I/O capability I/O controlled by DSP software or PLD logic General purpose PLD Use for peripheral glue logic to keypads, control panel, displays, LCDs, and other devices Over 3,000 gates of PLD with 16 macro cells Eliminate PLDs and external logic devices Create state machines, chip selects, simple shifters and counters, clock dividers, delays Simple PSDsoft ExpressTM development software, free from www.st.com/psm
Figure 1. TQFP 80-pin Package
TQFP80 (T)
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In-System Programming (ISP) with JTAG Program entire chip in 15-35 seconds with no involvement of the DSP Optionally links with DSP JTAG debug port Eliminate need for sockets and preprogramming of memory and logic devices ISP allows efficient manufacturing and product testing supporting Just-In-Time inventory Use low-cost FlashLINKTM cable with any PC. Available from www.st.com/psm. Content Security Programmable Security Bit blocks access of device programmers and readers Operating Range VCC: 3.3V 10%, Temp: 40 C to +85 C Zero-Power Technology 50uA standby current typical Flash Memory Speed, Endurance, Retention 120ns, 100K cycles, 15 year retention
August 2004
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