E-STE100P, STE100P

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STE100P
10/100 FAST ETHERNET 3.3V TRANSCEIVER
1 DESCRIPTION
Figure 1. Package The STE100P, also referred to as STEPHY1, is a high performance Fast Ethernet physical layer interface for 10Base-T and 100Base-TX applications. It was designed with advanced CMOS technology to provide a Media Independent Interface (MII) for easy attachment to 10/100 Media Access Controllers (MAC) and a physical media interface for 100Base-TX of IEEE802.3u and 10Base-T of IEEE802.3. The STEPHY1 supports both half-duplex and fullduplex operation, at 10 and 100 Mbps operation. Its operating mode can be set using auto-negotiation, parallel detection or manual control. It also allows for the support of auto-negotiation functions for speed and duplex detection.

TQFP64 (10x10x1.40mm)

Table 1. Order Codes
Part Number STE100P E-STE100P
(*)

Package TQFP64 TQFP64

(*) ECOPACK (see Section 9)

2

FEATURES

2.1 Industry standard IEEE802.3u 100Base-TX and IEEE802.3 10Base-T compliant Figure 2. Block Diagram
LEDS

Support for IEEE802.3x flow control IEEE802.3u Auto-Negotiation support for 10Base-T and 100Base-TX MII interface Standard CSMA/CD or full duplex operation supported Industrial temperature compliant

LEDS

100Mb/s
TX_CLK TXD[3:0] TX_ER TX_EN
Serial Management

TX Channel
Scrambler Parallel to Serial NRZ To NRZI Encoder
Binary To MLT3 Encoder TRANSMITTER 10/100 10 TX Filter
TXP TXN

4B/5B

10Mb/s

NRZ To Manchester Encoder

Link Pulse Generator

MDIO

Interface / Controller

MDC

REGISTERS

Auto Negotiation

Loopback

Clock Generation

System Clock

RXD[3:0] RX_ER RX_DV RX_CLK

MII

RX Channel 100Mb/s
4B/5B

Descrambler Code Align

Binary To MLT3 Decoder

Adaptive Equalization BaseLine Wander

Serial to Parallel

NRZI To NRZ Decoder

Clock Recovery

RECEIVER 10/100

RXP RXN

HW configuration pins

10Mb/s
HW Config Power Down

NRZ To Manchester Encoder

Link Pulse Detector

10 TX Filter Clock Recovery

SMART Squelch

February 2006

Rev. 19 1/31

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E-STE100P DATASHEET