E-STLC2500HSD| Datasheet

E-STLC2500HSD, E-STLC2500HSDTR, STLC2500HSD

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STLC2500HSD
Bluetooth mono headset solution V2.0 + EDR
Data Brief

Features

Based on Ericsson Technology Licensing Baseband Core (EBC) BluetoothTM specification compliance: V2.0 + EDR, HW ready for V2.1 (Lisbon)+ EDR Support ACL and SCO links Extended SCO (eSCO) links Faster Connection HW support for packet types ACL: DM1, DM3, DM5, DH1, DH3, DH5, 2DH1, 2-DH3, 2-DH5, 3-DH1, 3-DH3, 3-DH5 SCO: HV1, HV3 and DV eSCO: EV3, EV4, EV5, 2-EV3, 2-EV5, 3EV3, 3-EV5 Flexible and tunable application layer with support for up to 3 buttons, 3 LEDs, 1 vibrator Headset Profile 1.1 (HSP) Hands Free Profile 1.5 (HFP) Serial Port Profile (SPP) Significantly reduce headset production test time (typically less then 10 seconds including EEPROM writing) Adaptive Frequency Hopping (AFH) Transmit power Power Class 2 and Power Class 1.5 (above 4 dBm) Programmable output power Supports Pitch-Period Error Concealment (PPEC) Communication interfaces Fast UART up to 3 MHz for production testing PCM interface Up to 5 additional flexibly programmable GPIOs External interrupts possible through
GPIOs Fast I2C interface as master

WFBGA48

Clock support System clock input (digital or sine wave) at 9.6, 10, 13, 16, 16.8, 19.2, 26, 33.6 or 38.4 MHz Low power clock input at 3.2 kHz, 32 kHz and 32.768 kHz ARM7TDMITM CPU Memory organization On chip RAM, including provision for patches On chip ROM with a fully embedded solution for mono headsets up to the application layer Ciphering support up to 128-bit key Single power supply with internal regulators for core voltage generation Supports 1.65 V to 2.85 V I/O systems Auto calibration (VCO, filters)

Description
The STLC2500HSD is a fully embedded highly interoperable ROM-based solution in 0.13 um CMOS technology supporting the complete protocol stack, profiles and application layer to create low-cost high-performance Bluetooth mono headsets. It brings several advantages to the headset market such as a very fast reaction to interrupts, allowing a much better user experience, and the support of Pitch-Period Error Concealment (PPEC) an algorithm that works solely on the receiver side that permits to achieve a superior link quality and an extended range. A patch-RAM is available for ROM customization when required.

February 2008

Rev 1

1/5
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5

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