HCF4006| Datasheet

HCF4006, HCF4006BEY

Datasheet preview, take a look at Datasheets before downloading (Data Sheet is available on manufacturer site)

HCF4006B
18-STAGE STATIC SHIFT REGISTER
s

s s

PERMANENT REGISTER STORAGE WITH CLOCK LINE "HIGH" OR "LOW" ... NO INFORMATION RECIRCULATION REQUIRED FULLY STATIC OPERATION SHIFTING RATES UP TO 12MHzat 10V (Typ.) STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIFIED UP TO 20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25 C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B " STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES"

DIP

SOP

ORDER CODES
PACKAGE DIP SOP TUBE HCF4006BEY HCF4006BM1 T&R HCF4006M013TR

DESCRIPTION The HCF4006B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. The HCF4006B is comprised of 4 separate "shift register" sections; two sections of four stages and two sections of five stages with an output tap at the fourth stage. Each section has an independent "single rail" data path. A common clock signal is

used for all stages. Data is shifted to the next stage on negative going transitions of the clock. Through appropriate connections of inputs and outputs, multiple register sections of 4, 5, 8 and 9 stages or single register sections of 10, 12, 13, 14, 16, 17 and 18 can be implemented using one HCF4006B package. Longer shift register sections can be assembled by using more than one HCF4006B. To facilitate cascading stages when clock rise and fall times are slow, an optional output (D1+4') that is delayed one-half clock-cycle, is provided (see truth table for output from pin 2)

PIN CONNECTION

September 2001

1/8