M48Z128| Datasheet

M48Z128, M48Z128-70PM1, M48Z128Y, M48Z128Y-70PM1, M48Z128Y-85PM1

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M48Z128 M48Z128Y, M48Z128V*
5.0V OR 3.3V, 1 Mbit (128 Kbit x 8) ZEROPOWER SRAM
FEATURES SUMMARY

INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, AND BATTERY CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES 10 YEARS OF DATA RETENTION IN THE ABSENCE OF POWER BATTERY INTERNALLY ISOLATED UNTIL POWER IS FIRST APPLIED AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION WRITE PROTECT VOLTAGES: (VPFD = Power-fail Deselect Voltage) M48Z128: VCC = 4.75 to 5.5V 4.5V VPFD 4.75V M48Z128Y: VCC = 4.5 to 5.5V 4.2V VPFD 4.5V M48Z128V: VCC = 3.0 to 3.6V 2.8V VPFD 3.0V SOIC PACKAGE PROVIDES DIRECT CONNECTION FOR A SNAPHAT TOP WHICH CONTAINS THE BATTERY SNAPHAT HOUSING (BATTERY) IS REPLACEABLE PIN AND FUNCTION COMPATIBLE WITH JEDEC STANDARD 128K x 8 SRAMs EQUIVALENT SURFACE-MOUNT (SMT) SOLUTION REQUIRES A 28-PIN M40Z300/ W and A STAND-ALONE 128K x8 LPSRAM (SNAPHAT Top to be ordered separately)

Figure 1. 32-pin PMDIP Module

32 1

PMDIP32 (PM) Module

* Contact local ST sales office for availability.
February 2005 1/21