M48Z512A| Datasheet

M48Z512A, M48Z512A-70PM1, M48Z512AY, M48Z512AY-70PM1

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M48Z512A M48Z512AY, M48Z512AV
4 Mbit (512 Kbit x 8) ZEROPOWER SRAM
Features

Integrated, ultra low power SRAM, power-fail control circuit, and battery Conventional SRAM operation; unlimited WRITE cycles 10 years of data retention in the absence of power Automatic power-fail chip deselect and WRITE protection Two WRITE Protect voltages: (VPFD = power-fail deselect voltage) M48Z512A: VCC = 4.75 to 5.5V, 4.5V VPFD 4.75V M48Z512AY: VCC = 4.5 to 5.5V, 4.2V VPFD 4.5V M48Z512AV: VCC = 3.0 to 3.6V, 2.8V VPFD 3.0V Battery internally isolated until power is applied Pin and function compatible with JEDEC standard 512K x 8 SRAMs SOIC package provides direct connection for a SNAPHAT top which contains the battery SNAPHAT housing (battery) is replaceable Equivalent Surface-Mount (SMT) solution requires a 28-pin M40Z300/W and a standalone 128K x8 LPSRAM (SNAPHAT top to be ordered separately PMDIP32 is an ECOPACK package
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PMDIP32 (PM) Module

Description
The M48Z512A/Y/V ZEROPOWER RAM is a non-volatile, 4,194,304-bit Static RAM organized as 524,288 words by 8 bits. The devices combine an internal lithium battery, a CMOS SRAM and a control circuit in a plastic, 32-pin DIP Module. For Surface-Mount environments ST provides an equivalent SMT solution consisting of a 28-pin, 330mil SOIC NVRAM Supervisor (M40Z300/W) and a 32-pin, (Type II TSOP, 10 x 20mm) 4Mb LPSRAM. Both 5V and 3V versions are available (see Table 2 on page 7). The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surfacemount process. Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SNAPHAT battery package is shipped separately in plastic anti-static tubes or in Tape & Reel form. The part number is "M4Z32-BR00SH1.

December 2006

Rev 6

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