M54HC137| Datasheet

M54HC137, M54HC137K, M54HC137K1

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M54HC137
RAD-HARD 3 TO 8 LINE DECODER/LATCH (INVERTING)
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HIGH SPEED: tPD =18ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC = 2uA (MAX.) at TA=25 C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 54 SERIES 137 SPACE GRADE-1: ESA SCC QUALIFIED 50 krad QUALIFIED, 100 krad AVAILABLE ON REQUEST NO SEL UNDER HIGH LET HEAVY IONS IRRADIATION DEVICE FULLY COMPLIANT WITH SCC-9205-013

DILC-16

FPC-16

ORDER CODES
PACKAGE DILC FPC FM M54HC137D M54HC137K EM M54HC137D1 M54HC137K1

DESCRIPTION The M54HC137 is an high speed CMOS 3 TO 8 LINE DECODER/LATCH (INVERTING) fabricated with silicon gate C2MOS technology. This device is a 3 to 8 line decoder with latches on the three address inputs. When GL goes from low

to high, the addresses present at the select inputs (A, B, and C) is stored in the latches. As long as GL remains high no address changes will be recognized. Output enable pins G1 and G2, control the state of the outputs independently of the select or latch-enable inputs. All the outputs are high unless G1 is high and G2 is low. The 54HC137 is ideally suited for the implementation of glitch-free decoders in stored-address application in bus oriented systems. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

PIN CONNECTION

March 2004

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