M54HC138| Datasheet

M54HC138, M54HC138D, M54HC138D1, M54HC138K, M54HC138K1

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M54HC138
RAD-HARD 3 TO 8 LINE DECODER (INVERTING)
s

s s

HIGH SPEED: tPD = 13ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC = 4uA(MAX.) at TA=25 C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 54 SERIES 138 SPACE GRADE-1: ESA SCC QUALIFIED 50 krad QUALIFIED, 100 krad AVAILABLE ON REQUEST NO SEL UNDER HIGH LET HEAVY IONS IRRADIATION DEVICE FULLY COMPLIANT WITH SCC-9408-046

DILC-16

FPC-16

ORDER CODES
PACKAGE DILC FPC FM M54HC138D M54HC138K EM M54HC138D1 M54HC138K1

DESCRIPTION The M54HC138 is an high speed CMOS 3 TO 8 LINE DECODER fabricated with silicon gate C2MOS technology.

If the device is enabled, 3 binary select inputs (A, B, and C) determine which one of the outputs will go low. If enable input G1 is held low or either G2A or G2B is held high, the decoding function is inhibited and all the 8 outputs go high. Three enable inputs are provided to ease cascade connection and application of address decoders for memory systems. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

PIN CONNECTION

March 2004

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