M54HC164| Datasheet

M54HC164, M54HC164D, M54HC164K, M54HC164K1

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M54HC164
RAD-HARD 8 BIT SIPO SHIFT REGISTER
s

s s

HIGH SPEED: fMAX = 62MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =4uA(MAX.) at TA=25 C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 54 SERIES 164 SPACE GRADE-1: ESA SCC QUALIFIED 50 krad QUALIFIED, 100 krad AVAILABLE ON REQUEST NO SEL UNDER HIGH LET HEAVY IONS IRRADIATION DEVICE FULLY COMPLIANT WITH SCC-9306-041

DILC-14

FPC-14

ORDER CODES
PACKAGE DILC FPC FM M54HC164D M54HC164K EM M54HC164D1 M54HC164K1

DESCRIPTION The M54HC164 is an high speed CMOS 8 BIT SIPO SHIFT REGISTER fabricated with silicon gate C2MOS technology. The M54HC164 is an 8 bit shift register with serial data entry and an output from each of the eight

stages. Data is entered serially through one of two inputs (A or B), either of these inputs can be used as an active high enable for data entry through the other input. An unused input must be high, or both inputs connected together. Each low-to-high transition on the clock inputs shifts data one place to the right and enters into QA the logic NAND of the two data inputs (A x B), the data that existed before the rising clock edge. A low level on the clear input overrides all other inputs and clears the register asynchronously, forcing all Q outputs low. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

PIN CONNECTION

March 2004

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