M54HC165| Datasheet

M54HC165, M54HC165D, M54HC165K, M54HC165K1

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M54HC165
RAD-HARD 8 BIT PISO SHIFT REGISTER
s

s s

HIGH SPEED: tPD = 15ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =4uA(MAX.) at TA=25 C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 54 SERIES 165 SPACE GRADE-1: ESA SCC QUALIFIED 50 krad QUALIFIED, 100 krad AVAILABLE ON REQUEST NO SEL UNDER HIGH LET HEAVY IONS IRRADIATION DEVICE FULLY COMPLIANT WITH SCC-9306-042

DILC-16

FPC-16

ORDER CODES
PACKAGE DILC FPC FM M54HC165D M54HC165K EM M54HC165D1 M54HC165K1

DESCRIPTION The M54HC165 is an high speed CMOS 8 BIT PISO SHIFT REGISTER fabricated with silicon gate C2MOS technology. This device contains eight clocked master slave RS flip-flops connected as a shift register, with auxiliary gating to provide over-riding asynchronous parallel entry. Parallel data enters PIN CONNECTION

when the shift/load input is low. The parallel data can change while shift/load is low, provided that the recommended set-up and hold times are observed. For clocked operation, shift/load must be high. The two clock input perform identically; one can be used as a clock inhibit by applying a high signal; to permit this operation clocking is accomplished through a 2 input nor gate. To avoid double clocking, however, the inhibit signal should only go high while the clock is high. Otherwise the rising inhibit signal will cause the same response as rising clock edge. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

March 2004

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