M54HC237| Datasheet

M54HC237, M54HC237K

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M54HC237
RAD-HARD 3 TO 8 LINE DECODER LATCH
s

s s

HIGH SPEED: tPD = 16ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC = 4uA(MAX.) at TA=25 C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 54 SERIES 237 SPACE GRADE-1: ESA SCC QUALIFIED 50 krad QUALIFIED, 100 krad AVAILABLE ON REQUEST NO SEL UNDER HIGH LET HEAVY IONS IRRADIATION DEVICE FULLY COMPLIANT WITH SCC-9205-021

DILC-16

FPC-16

ORDER CODES
PACKAGE DILC FPC FM M54HC237D M54HC237K EM M54HC237D1 M54HC237K1

DESCRIPTION The M54HC237 is an high speed CMOS 3 TO 8 LINE DECODER fabricated with silicon gate C2MOS technology.

When GL goes from low to high, the address present at the select inputs (A, B, C) is stored in the latches. As long as GL remains high no address changes will be recognized. Output enable controls, G1 and G2 control the state of the outputs independently of the select or latch-enable inputs. All of the outputs are low unless G1 is high and G2 is low. The M54HC237 is ideally suited for the implementation of glitch-free decoders in stored-address applications in bus oriented systems. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

PIN CONNECTION

April 2004

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