M54HC393| Datasheet

M54HC393, M54HC393D, M54HC393K

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M54HC393
RAD-HARD DUAL BINARY COUNTER
s

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HIGH SPEED: fMAX = 79 MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =4uA(MAX.) at TA=25 C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 54 SERIES 393 SPACE GRADE-1: ESA SCC QUALIFIED 50 krad QUALIFIED, 100 krad AVAILABLE ON REQUEST NO SEL UNDER HIGH LET HEAVY IONS IRRADIATION DEVICE FULLY COMPLIANT WITH SCC-9204-074

DILC-14

FPC-14

ORDER CODES
PACKAGE DILC FPC FM M54HC14D M54HC14K EM M54HC14D1 M54HC14K1

DESCRIPTION The M54HC393 is an high speed CMOS DUAL BINARY COUNTER fabricated with silicon gate C2MOS technology. This counter circuit contains independent ripple carry counters and two 4-bit ripple carry binary

counters, which can be cascaded to create a single divide by 256 counter. Each 4-bit counter is increases during the high to low transition (negative edge) of the clock input, and each has an independent clear input. When CLEAR is set to low, all four bits of each counter are set to a low level. This enables count truncation and allows the implementation of divide by N counter configurations. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

PIN CONNECTION

May 2004

Rev. 1

1/12